1. Technical Field of the Invention
This present invention relates to integrated circuit design, and more particularly to synchronous and asynchronous sequential logic circuits and controlling critical races therein.
2. Background Art
Sequential logic circuits are heavily used in the implementation of very large scale integrated (VLSI) circuits. They appear as registers, as memory elements, as counters, in pseudo-random code generators and everywhere that data has to be manipulated such as in digital filters, data paths and logic operations. Therefore the improvement of such circuits such as a decrease in silicon area needed for implementation and/or a decrease in power consumption, without impairing other characteristics, is of prime importance to the VLSI industry. The resulting characteristics of the improved circuits would increase fabrication yield and/or increase the number of functions that can be implemented on the die.
Circuit size reduction also benefits conventional circuits that are too large or consume too much power to be efficiently used in VLSI circuits. For example, double edge-triggered D flip-flops (DETDFF) process data at both positive transition (low to high) and negative transition (high to low) of the clock. Compared to positive edge-triggered D flip-flop (PETDFF) which process data only at the positive transition of the clock, the DETDFF doubles the rate of data processing or, alternatively halves the clock rate thereby, either increasing the data throughput or reducing power consumption in the clock circuit respectively. However the implementation of conventional static DETDFF requires many gates and consumes too much silicon area to make them an attractive design alternative in VLSI circuits.
Sequential logic circuits are characterized by their structure that includes one or more feedback loops. The closed feedback loop xe2x80x9clatchesxe2x80x9d or xe2x80x9cstoresxe2x80x9d the present state of the circuit by closing the path returning the value of the circuit to its input. In synchronous sequential circuits, the opening and closing of the loop is controlled by a transition (low to high or high to low) of the clock waveform. The new value appears at the output node after a xe2x80x9cpropagation delayxe2x80x9d due to the elements in the loop, and is held, or xe2x80x9cmemorizedxe2x80x9d by the loop until the signal to accept a new value appears.
The flip-flop is the basic synchronous sequential circuit. Flip-flops appear in various configurations or xe2x80x9ctypesxe2x80x9d, such as D flip-flops, T flip-flops and J-K flip-flops where the D flip-flop is the most common. Flip-flops, of all three types, are usually configured as Master-Slave flip-flops, i.e. a sequential structure using two latches, called master and slave respectively, in cascade. A latch is the simplest sequential circuit containing a single feedback loop for storing one bit of data.
In the case of a positive edge-triggered D flip-flop (PETDFF), a positive clock transition, or positive edge, determines the output of the flip-flop as that value present at its input just before the clock transition. Thus for correct operation the input value has to be maintained to a stable value just before and just after the clock transition.
The correct operation of flip-flops is dependent on the time delays internal to the feedback loops with respect to the external input and clock waveforms. Excessive delay in the feedback loop can result in faulty operation of the flip-flop. In the conventional use of sequential logic circuits, the time delay of feedback loops is usually a small fraction of the periods of input data and of clock waveforms and does not interfere with the correct operation of the circuit. Also in a well-designed sequential circuit, only one value is present at both ends of an open loop before the loop closes. At the appropriate closing time the loop will then latch that value.
However when more than one value is input to a feedback loop, a critical race develops between the conflicting values. The final value latched in the circuit as result of the critical race depends on the internal delay of the loop. The internal delay of a logic circuit loop, although generally small with respect to the periods of data and clock, is not well defined, as this delay is dependent on the parasitic elements in the loop. These parasitic elements are due to the non-linear input and output capacitances of the transistors, capacitive coupling with other elements, interconnection and load capacitances and finite resistance and inductance of wiring and switching transistors when being activated (in the xe2x80x9conxe2x80x9d state).
One way to reduce the number of components in a master-slave flip-flop (M/S FF), and therefore reducing the required silicon area needed to implement it, consists of sharing a gate between the master latch and the slave latch. This eliminates one gate and its optional associated reset line. However sharing of the gate results in coupling between the feedback loops of the master and slave latches. This coupling between loops introduces critical races as the final state of the shared loop depends upon the value of which of the two latches will prevail and be the one to be latched. This critical race time interval is relatively small compared to the periods of clock and data, and is dependent upon the parasitic capacitances and resistances present in the coupled loop. The precise values of parasitic capacitances and resistances are unknown as they depend on the fabrication process. Thus, removing gates in the manner just described introduces critical races into the circuit, the final state of which is unknown.
This method, which introduces critical races, is therefore not practical or commercially viable. Accordingly, design practices for sequential logic circuits teach away from using critical race conditions in a circuit as this is assumed to create conditions that would make the circuit fail and/or generate unpredictable outcomes. Therefore present flip-flop configurations include additional circuitry to guarantee the absence of critical race conditions.
An additional way to avoid critical races is to have additional components to delay certain paths or to provide additional latching. However, as discussed herein, additional circuits increase power consumption and circuit area space.
In asynchronous sequential circuits critical races are also a problem, as no clock synchronization is used to close or open the feedback loop. In these circuits, as the feedback loop opens and closes under control of external signals unrelated to each other, more often than not more than one value is available instantaneously in the loop and critical races are often present.
Numerous approaches, such as unusual clocking and circuitry arrangements, have been used to eliminate race conditions and reduce circuit size. One example, U.S. Pat. No. 5,072,132, teaches a means of reducing circuit size by the use of a pulse generator coupled to the clock input of the latch. According to this design, a pulse generator produces sliver pulses correlating to the propagation delay through the latch of the state device circuits and thus purportedly enables a single latch to act as a flip-flop without racing. Alternatively, U.S. Pat. No. 4,841,168 teaches increasing circuit density by reducing gates, while avoiding racing. This is obtained by sharing a data gate between master and slave latches such that a latch gate of the master latch is shared by the slave latch as a data gate. Additionally, the clock signal is altered by changing the signal transmission speed of the clock on the slave side of the gate and adding control signals to the clock driver.
Additional background information on critical races can be found in xe2x80x9cFundamentals of Logic Designxe2x80x9d, by Charles H. Roth, Jr., West Publishing Company, 1992, Ch. 23, p. 602-603 and Ch. 25, p.629. Operation of a static double edge-triggered flip-flop is detailed in the paper: xe2x80x9cHigh-performance two-phase micropipeline building blocks: double edge triggered latches and burst mode select and toggle circuitsxe2x80x9d by Yun, K. Y., Beerel, P. A. and Arceo, J. in IEE Proc., Circuits, Devices, Syst., 1996, 143,(5),pp.282-288.
As can be seen, attempts to reduce circuit size have not only been frustrated by the risk of critical races, but the solutions to the problem of critical races generally involves complication of the circuit""s clocking arrangement or the addition of other circuitry to enable the device. What is needed therefore, is a method and apparatus for controlling critical races in sequential circuits that facilitates implementation of circuits with fewer gates and on smaller silicon area without the need of adding components or implementing compensatory clocking schemes.
The invention is devised in the light of the problems of the prior art described herein. Accordingly it is a general object of the present invention to provide a novel and useful technique that can solve the problems described herein.
In addition, the critical race control techniques of the present invention give rise to configurations of sequential integrated circuits with less area and lower power dissipation than conventional implementations. The techniques of the present invention also simplifies the design of asynchronous circuits by solving the problem of critical races.
Critical race control reduces the number of logic gates necessary to implement the circuit by sharing some gates and circuit paths among data latches. This technique achieves a corresponding reduction in required silicon area while controlling the result of critical races thus enabling the circuit to function properly. In addition, the resulting sequential circuits, as disclosed herein, consume less power in some applications.
Methods and apparatus for implementing critical race control in sequential circuits are disclosed herein. Critical race control meets the needs identified herein by adjusting the relative delay of the individual sections of the shared feedback loop with respect to one another through adjustment of the resistance of the transmission gate in each section thereby adjusting the delay of the loop section in which the transmission gate is embedded.
The effect of this regulation is the control of critical races by ensuring that only data from the desired input is allowed to determine a given gate""s output when two or more different data exists on a shared circuit paths. This enables the design and implementation of sequential circuits having fewer gates than found in conventional circuit designs of equivalent function.
Critical race control may be used in a wide range of applications, particularly those involving static sequential circuits. As described herein, critical race control may be readily embodied in the commonly used master-slave edge-triggered flip-flop circuits. Examples of embodiments include a D flip-flop, a static shift register and a static double-edged-triggered D flip-flop circuit for applications wherein data and clock rates are equivalent. In addition, an embodiment of an integrated shift right-shift left register with smaller number of gates than the conventional implementation of that function is also included.
Critical race control (CRC) can be successfully applied to facilitate the design of asynchronous circuits by eliminating the concern for critical races, therefore obtaining circuits with a lower number of gates as compared to present implementation methods. An example is presented using CRC for the implementation of an asynchronous circuit containing critical races that cannot be implemented with present methods. These embodiments exemplify the wide range of use and flexibility of this new technique.
The effective delay in a transmission path section, can be changed by altering its time constant through modification of its resistance, and/or its capacitance or by varying the current and voltages charging and discharging the various elements in the path or still, by changing the threshold voltages of the logic gates in the loop. In practice a combination of some or all of the above methods, including varying power supplies, clock rates and other parameters may be used. In VLSI circuits the designer has almost no control on the parasitic capacitances except for the desire to minimize them, therefore it is easier to modify the resistances in the paths. Fortunately, the resistance of the transmission gate can be easily and robustly regulated by adjusting the size of its constituent transistors during design.
In large VLSI dies there are variations in transistors parameters due to the non-uniformity of the VLSI fabrication process over the size of the die. Changes in local environmental and electrical conditions on large dies, such as high local temperature (xe2x80x9chot spotsxe2x80x9d) and local supply voltage variations, will also induce variations in the operating conditions of individual transistors, and therefore on circuits, at different locations on the die. Therefore circuits relying on absolute relations between parameters of transistors for correct operation are not robust and cannot operate over a wide range of environmental and process fabrication parameters. Critical race control, as described herein relies on the ratio of resistance of only two transmission gates that are in very close physical proximity to one another as they are in the same loop of the same flip-flop. Under this condition of close proximity, both the transistor parameters and variations in environmental and electrical conditions will, for all practical purposes, be identical in both transmission gates.
Accordingly by establishing a desired ratio between the resistances of the proximate transmission gates, it is possible to reliably control the delay in various sections of the loop and control the outcome of a critical race.
This technique can be used with all other master/slave implementations. For example, U.S. Pat. No. 5,497,114 describes a master-slave flip-flop that uses single pass transistors to replace the conventional transmission gate used in a flip-flop. The critical race control can be used on that type of flip-flop too to reduce the number of gates.
An object of the invention is a method for producing efficient integrated sequential circuits, comprising the steps of providing at least one data input signal and at least one clock signal, and designing one or more circuit loops each having a plurality of sections and two or more switches wherein the switches in the loops separate between the sections. Another step is controlling a critical race of the loops by adjusting a relative delay of the sections.
An additional object is the method for producing efficient integrated sequential circuits, wherein the switches are one or more transistors and the relative delay is regulated by adjusting transistor dimensions, such as length and width. In another embodiment the relative delay is regulated by adjusting a resistance or capacitance of the transistors. Alternatively, the switches are transmission gates and the relative delay is regulated by adjusting a resistance/capacitance (RC) time constant of the transmission gates.
A further object is the method for producing efficient integrated sequential circuits, wherein the relative delay is adjustable by external parameters. Although not inclusive, the external parameters include clock frequencies, supply voltages (Vdd), ground supplies (Vss), bias voltages, and temperature. A further embodiment relates to the relative delay that is dynamically controllable by the external parameters. Such dynamic control allows for changing the delay and altering the critical race conditions.
Along this same line, another object is the method for producing efficient integrated sequential circuits, wherein the switches are transmission gates and the relative delay is regulated by adjusting a set of fabrication process parameters directly or indirectly effecting the transmission gates. Such fabrications include doping concentration, implant concentration, threshold voltage, polysilicon dimensions, polysilicon composition, substrate dimensions, diffusion dimensions, metal dimensions and oxide dimensions. The direct effects would be applicable based upon changes to the transmission gates itself, while the indirect effects would effect other logic circuits that are interconnected to the transmission gates.
And an additional object is the method for producing efficient integrated sequential circuits, wherein the switches are transistors and further comprising the step of locating the transistors in close proximity. Such proximity avoids differences in transistors and more certainty when regulating the relative delay.
An object includes the method for producing efficient integrated sequential circuits, wherein the relative delay is a first propagation delay in a first section as compared to a second propagation delay in a second section, wherein the first and second section are within the same loop or coupled loops.
In addition, the method for producing efficient integrated sequential circuits, wherein said relative delay is introduced by resistors within the section. Another object further comprising logic circuits in the sections, and wherein the logic circuits provide the relative delay. Any of the components in the sections can be used to establish the proper relative delay.
And yet another object is the method for producing efficient integrated sequential circuits, wherein integrated circuits are from the group comprising single edge-triggered flip-flops, double edge-triggered flip-flops, D flip-flops, T flip-flops, J-K flip-flops, binary memory elements and S-R flip-flops. Also including efficient integrated sequential circuits, wherein integrated circuits are from the group comprising flip-flops-based registers, shift registers, counters, pseudo random generators, memory devices.
An object also includes the method for producing efficient integrated sequential circuits, wherein a data flow is in more than two directions, such as forward and reverse.
An object of the invention is a sequential circuit comprising a data input, a data output, a loop with a plurality of sections coupled to the data input and the data output. There is a means for controlling a critical race by adjusting a relative time delay between the plurality of sections.
Additionally, the sequential circuit, wherein the means for controlling is changing a ratio of a resistance/capacitance (RC) time constant between the sections. Also, further comprising two or more transmission gates and a plurality of logic devices connected in the loop and wherein the relative time delay is a difference in propagation time delay between the sections of the loop. Accordingly, one of the means for controlling is a ratio of resistance of the sections of the loop. The relative delay is also established where the ratio of resistance is between the transmission gates of the sections. And, wherein the relative delay is between the logic devices of the sections. Furthermore, wherein the relative time difference is changed by adjusting a size of the transmission gates size of capacitance of the sections.
An object of the invention is a sequential circuit comprising a data input, a first loop with a plurality of first loop sections, wherein the first loop is coupled to the data input, and a second loop with a plurality of second loop sections, wherein the second loop is coupled to the first loop. An output node is coupled to the first and second loop such that the output is derived from either loop. There is a means for controlling a critical race between the first loop sections and between the second loop sections by adjusting a relative time delay between the first loop sections and between the second loop sections.
Yet an additional object is the sequential circuit, wherein the means for controlling is changing a ratio of a resistance/capacitance (RC) time constant between the first loop sections and the second loop sections. The sequential circuit, further comprising two or more transmission gates and a plurality of logic devices connected in the first loop and comprising two or more transmission gates and a plurality of logic devices connected in the second loop, and wherein the relative time delay is a difference in propagation time delay between the sections of the first loop and the sections of the second loop. And, the means for controlling is a ratio of resistance of the sections of the first loop and the sections of the second loop. Or, the ratio of resistance is between the transmission gates of the sections of the first loop and the transmission gates of the sections of the second loop, either individually or coupled loops.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein we have shown and described only a preferred embodiment of the invention, simply by way of illustration of the best mode contemplated by us on carrying out our invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention.